The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a logic delay circuit.
Heretofore, a semiconductor integrated circuit has been more and more required to have high integration density, and according to the requirement, a micro-fine working technique has been developed. In addition, realization of a high integration density is being investigated with respect to the aspect of layout to avoid a dead space in the arrangement of circuit elements on a semiconductor substrate. For a circuit of a plurality of series-connected insulated gate field effect transistors (hereinafter abbreviated as MOST's) with a source and a drain, respectively, of adjacent MOST's connected in common, also a high integration density must be realized. Especially, for a CMOS inverter circuit of a plurality of n-channel type insulated gate field effect transistors (hereinafter abbreviated as nMOST's) and a plurality of p-channel type insulated gate field effect transistors (hereinafter abbreviated as pMOST's), also likewise a high integration density must be realized. Such CMOS inverter is frequently used in a logic delay circuit.